It has become common to integrate a phase-locked loop (PLL) onto an integrated circuit (IC) in order to synchronize the operating frequency of the PLL, and hence the integrated circuit, to an external clock signal (“PLL mode”). As shown in FIG. 1, the integration of a PLL generally requires an IC to have two additional pins (alternatively termed “terminals” or “nodes”): a PLLIN pin for an external clock input and a PLLLPF pin for connection of a PLL frequency compensation/loop filter such as an R-C network. Minimizing pin count, however, is preferred in order to reduce packaging size and complexity, and improve yield.
FIG. 2 shows an example of a conventional PLL of a type implemented in such circuits. A PLL 10 generally comprises a phase detector 12, and voltage-controlled oscillator (VCO) 14 connected to phase detector 12 through the PLLLPF pin to which frequency compensation external filter 16 comprising a resistor RLP and capacitor CLP is connected. Phase detector 12 compares the phase and frequency of the external clock from the PLLIN pin with those of an internal clock generated by VCO 14. The output of phase detector 12 (“error signal”) may be produced by a pair of complementary current sources that charge or discharge external filter 16 connected to the PLLLPF pin. The PLLLPF pin is provided to PLL 10 so that a user can choose a desired resistance and capacitance to set the PLL's characteristics.
If the external frequency is greater than the internal frequency, current is sourced continuously to filter 16, pulling up the PLLLPF pin. When the external frequency is less than that of the internal frequency, current is sinked continuously, pulling down the PLLLPF pin. If the external and internal frequencies are the same but exhibit a phase difference, current is sourced or sinked for an amount of time corresponding to the phase difference. The voltage on the PLLLPF pin is adjusted until the phase and frequency of the internal clock become identical to those of the external clock. At the stable operating point, the phase comparator output is high impedance and capacitor CLP holds the voltage. Resistor RLP and capacitor CLP of the external filter 16 smooth out the current pulses from phase detector 12 and provide a stable input to VCO 14. Resistor RLP and capacitor CLP determine how fast the loop acquires lock.
When the IC is not synchronized to the external clock, the frequency of the internal clock may be set by applying a DC voltage to the PLLLPF pin (“tri-state mode”). For example, it has been known to use the PLLLPF pin to digitally select the integrated circuit's operating frequency by tying the PLLLPF to a high voltage supply (e.g., VCC) or a low voltage supply (e.g., GND) to select maximum frequency fmax or minimum frequency fmin of VCO 14. FIG. 3 shows an example of the relationship between a voltage on the PLLLPF pin and frequency of the internal clock to be generated by VCO 14. The level of voltage on the PLLLPF pin dictates the frequency of the internal clock.
The PLLLPF pin can also be floated (left in a high impedance state) to select a mid-range frequency fmid shown in FIG. 3. This mid-range frequency fmid can be achieved internally on the IC, for example, by weakly tying the PLLLPF pin through a high resistance or weak active device to a voltage reference equal to the center of the VCO's voltage range. Accordingly, the PLLLPF pin can be used as a digital (or tri-state) pin to select one of two (or three) discrete operating frequencies, while requiring no additional external components. The following table shows a relationship between inputs to PLLIN and PLLLPF pins and a frequency of the internal clock.
PLLINPLLLPFFrequencyExternal clockR-C to GNDPhase-locked to external clock—Tied to GNDfmin—Floatfmid—Tied to VCCfmax
Alternatively, the PLLLPF pin can be used as an analog voltage input to select any of the VCO's frequencies (see FIG. 3). This requires a precision external reference to be generated, for example, by a resister divider on a power supply or other voltage reference. However, even if a precision voltage reference of the desired value is readily available, the gain (or slope) of the curve in FIG. 3 (the VCO's linear region) typically varies from part to part (due to manufacturing variations) and over temperature. Therefore, a voltage to be applied to the PLLLPF pin needs to be generated accurately.
The PLL mode and tri-state mode are described in the datasheet of commercially available LTC 3701 2-phase, low input voltage, dual step-down DC/DC controllers, manufactured by Linear Technology Corporation, incorporated herein by reference.
FIGS. 4 and 5 show another common way to select an ICs operating frequency, in which a resistor RT or capacitor CT is connected between a frequency select/set pin (commonly denoted as “FSET,” “RT,” or “CT” pin) and ground (or a supply rail). This allows for the IC's frequency to be selected in an analog manner (based on the value of resistor RT or capacitor CT) from a continuous range of possible frequencies (“passive element setting mode”).
For example, a voltage is applied across resistor RT, and a scaled version of the resultant current is then used as the input current of a current controlled oscillator (“ICO”), an output frequency of which is a function (usually proportional) of the input current. The frequency of the internal clock to be generated by the ICO can be selected relatively precisely, since the voltage forced across resistor RT can be, or be derived from, a precision voltage reference such as a bandgap reference. The value of an external resistor can also be very accurate (e.g., 1% resistors are common). FIG. 6 shows the relationship between frequency of the internal clock to be generated and value of resister RT. When the value of resistor RT increases, the current flowing in the resistor decreases. Therefore, the frequency of the internal clock to be generated by the ICO decreases. When the value of resistor RT decreases, the current flowing in the resistor increases. Therefore, the frequency of the internal clock to be generated by the ICO increases.
An example using resistor RT is described in the datasheet of commercially available LTC 3412 monolithic synchronous step-down regulators, manufactured by Linear Technology Corporation, incorporated herein by reference.
Capacitor CT typically serves as a timing element for the IC's oscillator, such that the IC's frequency is inversely proportional to the value of the capacitor. Using a capacitor CT for this purpose is described in the datasheet of commercially available LTC 1735 high efficiency synchronous step-down switching regulator, manufactured by Linear Technology Corporation, incorporated herein by reference.
This disclosure addresses the desirability of a combination of the PLL mode, tri-state mode and passive element setting mode into an IC, with minimum pins (terminals, nodes), for controlling those modes.